The NY ComSoc chapter hosted a seminar on Nov 30, 2021. The title of the presentation is “Algorithm and Hardware Co-Design for Energy-Efficient Deep Learning”, by Prof. Bo Yuan. The event is co-hosted by New Jersey Coast Section Chapter.

Date: Friday Oct 29, 2021

Time: 7pm – 8:15pm Eastern Time (US & Canada)

Location: New York, USA

vTool event page:

Primary Host: New York Section Chapter,COM19


New Jersey Coast Section Chapter, COM19

Event Agenda

06:45 PM – 07:00 PM: Connecting to the ZOOM meeting

07:00 PM – 07:05 PM: Welcoming & IEEE ComSoc Membership Promotion (policies, abstract)

07:05 PM – 07:10 PM: Speaker Introduction

07:10 PM – 07:55 PM: Presentation (45 minutes)

07:55 PM – 08:10 PM: Questions and Answers (15 minutes)

08:10 PM – 08:15 PM: Closing Remarks

Talk Title

Algorithm and Hardware Co-Design for Energy-Efficient Deep Learning


In the emerging artificial intelligence era, deep neural networks (DNNs), a.k.a. deep learning, have gained unprecedented success in various applications. However, DNNs are usually storage intensive, computation intensive and very energy consuming, thereby posing severe challenges on the future wide deployment in many application scenarios, especially for the resource-constraint low-power IoT application and embedded systems. In this talk, I will introduce the algorithm/hardware co-design works for energy-efficient DNN in my group. First, I will show the use of low displacement rank (LDR) matrices and low-rank tensor can enable the construction of low-complexity DNN models as well as the corresponding energy-efficient DNN hardware accelerators. In the second part of my talk, I will show the benefit of using structured and unstructured sparsity of DNN for designing low-latency and low-power DNN hardware accelerators.

Speaker Bio

Dr. Bo Yuan is currently the assistant professor in the Department of Electrical and Computer Engineering in Rutgers University. Before that, he was with City University of New York from 2015-2018. Dr. Bo Yuan received his bachelor and master degrees from Nanjing University, China in 2007 and 2010, respectively. He received his PhD degree from University of Minnesota, Twin Cities in 2015. His research interests include algorithm and hardware co-design and implementation for machine learning and signal processing systems, error-resilient low-cost computing techniques for embedded and IoT systems and machine learning for domain-specific applications. He is the recipient of Global Research Competition Finalist Award in Broadcom Corporation. Dr. Yuan serves as technical committee track chair and technical committee member for several IEEE/ACM conferences. He is the associated editor of Springer Journal of Signal Processing System.

Total Registration: 73 (as of 11/30/2021)

Peak attendance: 56

Presentation Video

Presentation Slides